This invention relates to semiconductor memory devices and more particularly to an improved intermediate output buffer for an MOS memory device.
The most widely used semiconductor memory device at present is the N-channel MOS dynamic RAM of the type disclosed in U.S. Pat. No. 3,940,747, issued Feb. 24, 1976 to C-K Kuo and N. Kitagawa, assigned to Texas Instruments, where a "4K" or 4096 bit random access memory is described. This device is also shown at pp. 116-121 in the Sept. 13, 1973 issue of Electronics. Higher density dynamic RAM's are shown in Electronics, Feb. 19, 1976, pp. 116-121, and May 13, 1976, pp. 81-86, where "16K" or 16384 bit memory devices are described. Our pending U.S. patent application Ser. No. 691,734, filed June 1, 1976, assigned to Texas Instruments, likewise shows a 16K RAM.
In these prior dynamic RAM's the data output is usually taken from one side of a column line, and data input is to the same side, even though the addressed cell is on the opposite side. In high density devices such as the 16K, the capacitance of the column lines or sense lines is high, resulting in delay due to the time required for the lines to charge or discharge to full logic levels. It is therefore preferable to sense the logic levels on the column lines, on each side of the sense amplifiers, and generate high level outputs, by means of intermediate output buffers.
It is therefore the principal object of the invention to provide an improved semiconductor memory device which operates at higher speed or shorter access time.
Another object is to provide an intermediate output buffer which speeds up the transfer of data from a cell array to the output terminal of a memory device.